In this modern day and age, people have become more concerned with gadgets, equipment or tools that are efficient yet can conserve energy at the same time. In line with this, the data-dependent write-assist dynamic (DDWAD) SRAM (a faster type of memory chip that requires less power than dynamic memory) cell has been proposed to reduce the power consumption and enhance the reliability against process, voltage, temperature variation and aging effect under static stress. How is this possible? Basically, the cell has distinct read and write circuits with single bit line for respective operations which improve the read stability. In the cell, write operation is performed using separate write signal WS instead of wordline WL. The write signal WS is introduced to reduce the discharging activity at the write bit line BL to reduce the dynamic power consumption. In addition, the latch property of the cell is disabled during write operation to flip the data faster at the storage nodes. The proposed cell consumes approximately 60.4 % lower write power and 52.8 % read power compared to the other cells. The storage node does not float during read operation and thus cell is not sensitive to any positive noise. The data in the cell can be maintained even if the power supply is reduced to 300 mV.